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pci to isa bridge set w83628f & W83629D preliminary publication release date: dec 1998 - 1 - revision 0.32 general description w83628f is a pci-to-isa bus conversion ic. W83629D is a condensed centralizer ic for irq and dma control. w83628f and W83629D together form a complete set for the pci-to-isa bridge. for the new generation intel chipset camino and whitney, featuring lpc bus, there is no support for isa bus and slots. however the demand of isa devices still exist. for such case, w83628f plus W83629D are the best companion solution for the non-isa chipset. also the packages of w83628f (128-qfp) and W83629D (48- lqfp) had been chosen to be the most economic solution for save the m/b board layout size and cost. for the new generation chipset featuring lpc interface and support no isa bus, w83627hf/f (winbond lpc i/o) together with the set of w83628f and W83629D is the complete solution. features pci to isa bridge full isa bus support including isa masters 5v isa and 3.3v pci interfaces pc/pci dma protocol for software transparent irq serializer for isa parallel irq transfer to serial irq supports 3 fully isa compatible slots without buffering pci bus at 25mhz, 33mhz and up to 40mhz supports programmable isa bus divide the pci bus clock into 3 or 4 all isa signals can be isolate supports configuration registers for programming performance package 128-pin pqfp for w83628f 48-pin lqfp for W83629D
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 2 - revision 0.32 block diagram of w83628f frame# trdy# ad[31:0] c/be[3:0]# par irdy# stop# devsel# idsel serr# pci interface bale aen isa interface sa[19:0] sd[15:0] iochrdy iocs16# iochk# ior# iow# la[23:17] sbhe# memcs16# memr# memw# smemr# smemw# zerows# master# refresh# nogo pcirst# pciclk rstdrv sysclk isolate# signal isolation control power suppiy 3.3v 5v handshaking hs[2:0] romcs#
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 3 - revision 0.32 block diagram of W83629D dreq[7:5,3:0] isareq# isagnt# pci/pci interface tc power suppiy 3.3v 5v dack[7:5,3:0]# pcirst# pciclk pci host & bridge set handshaking logic hs[2:0] irq[15,14,12:9,7:3] serirq serial to parallel irq nogo
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 4 - revision 0.32 pin configuration for 628f 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 l a 2 0 l a 2 1 l a 2 2 l a 2 3 m e m r # l a 2 2 m e m w # s d 8 s d 9 s d 1 0 s d 1 1 s d 1 2 s d 1 3 s d 1 4 s d 1 5 m a s t e r # s b h e # v c c g n d a d 3 1 a d 3 0 a d 2 9 a d 2 8 a d 2 7 a d 2 6 3 v c c a d 2 5 a d 2 4 i d s e l c / b e 3 # a d 2 3 a d 2 2 a d 2 1 a d 2 0 a d 1 9 a d 1 8 a d 1 7 a d 1 6 g n d s d 6 s d 7 s y s c l k s a 1 9 s a 1 8 s a 1 7 g n d s a 1 6 s a 1 5 s a 1 4 s a 1 3 s a 1 2 s a 1 1 s a 1 0 s a 7 v c c s a 9 s a 6 v c c s a 4 s a 3 s a 2 a d 0 s a 1 s a 0 r e f r e s h # n o g o r s t d r v c s # i s o l a t e p c i r s t # a d 1 a d 2 a d 3 g n d c/be2# frame# irdy# trdy# devsel# stop# pciclk 3vcc par c/be1# gnd ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 pclk_out c/be0# ad7 ad6 ad5 3vcc s a 5 s a 8 zerows# iochk# sd4 sd5 sd0 sd1 sd2 sd3 hs0 hs2 smemw# aen smemr# iochrdy gnd hs1 iow# memcs16# gnd la19 la18 la17 bale iocs16# ior# vcc w83628f a d 4 serr# # r o u
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 5 - revision 0.32 pin configuration for 629d irq15 vcc drq0 dack1# hs0 hs1 hs2 gnd tc dack0# drq1 dack2# W83629D 1 12 13 24 25 36 37 48 3vcc pcirst# serirq nc pciclk gnd isagnt# isareq# nogo nc nc nc n c d r q 5 d a c k 5 # g n d d r q 3 a c k 3 v c c d r q 2 d d a c k 6 # d r q 6 d r q 7 d a c k 7 # i r q 3 c v c d g n d i r q 4 i r q 5 i r q 6 i r q 7 i r q 9 i r q 1 i r q 1 i r q 1 i r q 1 0 1 2 4
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 6 - revision 0.32 1. pin description note: please refer to section 13.2 dc characteristics for details. i/o 12t - ttl level bi-directional pin with 12 ma source-sink capability i/o 24t - ttl level bi-directional pin with 24 ma source-sink capability i/o 12tp3 - 3.3v ttl level bi-directional pin with 12 ma source-sink capability i/o 24tp3 - 3.3v ttl level bi-directional pin with 24 ma source-sink capability i/od 12t - ttl level bi-directional pin open drain output with 12 ma sink capability i/o 24t - ttl level bi-directional pin with 24 ma source-sink capability out 12t - ttl level output pin with 12 ma source-sink capability out 24t - ttl level output pin with 24 ma source-sink capability out 12tp3 - 3.3v ttl level output pin with 12 ma source-sink capability out 24tp3 - 3.3v ttl level output pin with 24 ma source-sink capability od 12 - open-dra in output pin with 12 ma sink capability od 24 - open-drain output pin with 24 ma sink capability in cs - cmos level schmitt-trigger input pin in t - ttl level input pin in td - ttl level input pin with internal pull down resistor in ts - ttl level schmitt-trigger input pin in tsp3 - 3.3v ttl level schmitt-trigger input pin 1. 1 w83628f pin description 1. 1 .1 pci interface symbol pin i/o function ad[31:0] 19-26 30-37 52-59 61-63 66-70 i/o 24tp3 pci bus address and data signals. the standard pci address and data lines. address is driven with frame# assertion, data is driven or received in following clocks. c/be[3:0]# 28,45 51,60 i/o 24tp3 pci bus command and byte enables. during the address phase of a transaction c/be[3:0]# define the bus command. during the data phase c/be[3:0]# are used as byte enables. pciclk 47 in t pci bus system clock . pciclk provides timing for all transactions on the pci bus. all other pci signals are sampled on the rising edge of pciclk, and all timing parameters are defined with respect to this edge. pclk_out 48 out 12t pci bus system clock dpll output. the pclk_out can reduce the pciclk loading and it produced from internal dpll.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 7 - revision 0.32 1.1.1 pci interface, continued symbol pin i/o function frame# 40 i/o 24tp3 frame signal . frame# is driven by the current pci bus master to indicate the beginning and duration of an access. idsel 29 in t initialization device select. idsel is used as a chip select during configuration read and write transactions. this signal should be externally tied to one of the upper 21 address signals. stop# 39 i/o 12tp3 bus stop#. stop# indicates the current target is requesting the master to stop the current pci bus transaction. irdy# 41 i/o 12tp3 initiator ready. irdy# indicates the initiating agent ability to complete the current data phase of the pci bus transaction. trdy# 42 i/o 12tp3 target ready. trdy# indicates the target agent ?s ability to complete the current data phase of the pci bus transaction. devsel# 43 i/o 12tp3 device select. w83628f drives devsel# to indicate that it is the target of the current pci bus transaction. w83628f uses subtractive decoding and the nogo protocol to claim pci transactions. serr# 45 od 12 system error. serr# can be pulsed active by any pci agent that detects a system error condition. par 49 i/o 12tp3 parity signal. w83628f generates even parity across ad[31:0] and c/be[3:0]#. pcirst# 71 in t pci reset. w83628f receives pcirst# as a reset from the pci bus. 1. 1 .2 control logic and handshaking signals symbol pin i/o function hs[2:0] 112- 114 i/o 12 handshaking signals. hs[2:0] connected to W83629D for pci to isa set handshaking signals. hs1 is handshaking signal 1, this pin weak pulled-down during pcirst# is asserted, and apply a pull-up resistor(4.7kohm) to this pin disables isa bridge subtraction decoder. isolate# 72 in t isolation control input. isolate# is an active low signal by user programming to control the w83628f all output signals to isolation and tri-state. nogo 76 in t nogo, this signal indicates which master initiated the current transaction and also indicates whether or not the current bus cycle is targeted for the isa bus. this signal is a point-to-point connection between pci host bridge and w83628f.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 8 - revision 0.32 1. 1 .3 isa interface signals symbol pin i/o function sa[19:17] 98-96 out 24t system address bus. these are the upper address lines that define the isa ?s byte granular address space (up to 1 mbyte). sa[19:17] are at an unknown state upon pcirst#. sa[16:0] 94-83 81-77 i/o 24t system address bus. these are the bi-directional lower address lines that define the isa ?s byte granular address space (up to 1 mbyte). sa[16:0] are at an unknown state upon pcirst#. sd[15:0] 110- 107, 104, 103, 101, 100, 8-15 i/o 24t system data. sd[15:0] provide the 16-bit data path for devices residing on the isa bus. the w83628f tri-states sd[15:0] during pcirst#. aen 118 out 24t address enable. aen is asserted during dma cycles. this signal is also driven high during w83628f initiated refresh cycles. aen is driven low upon pcirst#. ior# 120 i/o 24t i/o read. ior# is the command to an isa i/o slave device that the slave may drive data on to the isa data bus (sd[15:0]). iow# 121 i/o 24t i/o write. iow# is the command to an isa i/o slave device that the slave may latch data from the isa data bus (sd[15:0]). iochrdy 116 i/o 24t i/o channel ready. resources on the isa bus negate iochrdy to indicate that additional time (wait states) is required to complete the cycle. sysclk 99 out 24t isa system clock. sysclk is the reference clock for the isa bus. the sysclk is generated by dividing pciclk by 3 or 4. rstdrv 74 out 24t reset drive. w83628f asserts rstdrv to reset devices that reside on the isa bus. the w83628f asserts this signal while the pcirst# is asserted. iocs16# 124 in t 16-bit i/o chip select. this signal is driven by i/o devices on the isa bus to indicate that they support 16-bit i/o bus cycles. sbhe# 18 i/o 24t system byte high enable. sbhe# asserted indicates that a byte is being transferred on the upper byte (sd[15:8]) of the data bus. sbhe# is at an unknown state upon pcirst#. iochk# 105 in t i/o channel check. iochk# can be driven by any resource on the isa bus during on detection of an error.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 9 - revision 0.32 1.1.3 isa interface, continued symbol pin i/o function memr# 6 i/o 24t memory read. memr# asserted indicates the current isa bus cycle is a memory read. memw# 7 i/o 24t memory write. memw# asserted indicates the current isa bus cycle is a memory write. master# 17 in t master#. this signal is used with a dreq line by an isa master to gain control of the isa bus. la[23:17] 5-2 127- 125 i/o 24t unlatched address. the la[23:17] address lines are bi- directional. these address lines allow accesses to physical memory on the isa bus up to 16 mbytes. la[23:17] are outputs when the w83628f owns the isa bus. romcs# 73 i/o 12 romcs# ,this pin weak pulled-down during pcirst is asserted, and apply a pull-up resistor (4.7 kohm) to this pin enable positive decoder of bios address range (depend on configure register 70 , bit 3,2). when bios assress range is enabled , the pin is bios rom cs# output. refresh# 75 i/o 24t refresh. refresh# asserted indicates that a refresh cycle is in progress, or that an isa master is requesting w83628f to generate a refresh cycle. upon pcirst#, this signal is tri-stated. zerows# 106 in t zero wait states. an isa slave asserts zerows# after its address and command signals have been decoded to indicate that the current cycle can be executed as an isa zero wait state cycle. zerows# has no effect during 16-bit i/o cycles. smemr# 117 out 24t standard memory read. smemr# asserted indicates the current isa bus cycle is a memory read cycle to an address below 1 mbyte. smemw# 119 out 24t standard memory write. smemw# asserted indicates the current isa bus cycle is a memory write cycle to an address below 1 mbyte. bale 122 out 24t bus address latch enable. bale is an active high signal asserted by the w83628f to indicate that the address (sa[19:0], la[23:17]) and sbhe# signal lines are valid. the la[23:17] address lines are latched on the trailing edge of bale. bale remains asserted throughout dma and isa master cycles. bale is driven low upon pcirst#. memcs16# 123 od 24 memory chip select 16. memcs16# asserted indicates that the memory slave supports 16-bit accesses. 1. 1 .4 power signals symbol pin i/o function vcc 1, 82, 102, 115 pwr 5v supply. 3vcc 27, 46, 64 pwr 3.3v supply.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 10 - revision 0.32 gnd 16, 38, 50, 65, 95, 111, 128 pwr ground.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 11 - revision 0.32 1. 2 W83629D pin description 1. 2 .1 control logic and handshaking signals symbol pin i/o function hs[2:0] 17-15 i/o 12 handshaking signals. hs[2:0] connected to w83628f for pci to isa set handshaking signals. nogo 40 in t no go. this signal indicates which master initiated the current transaction and also indicates whether or not the current bus cycle is targeted for the isa bus. this signal is a point-to-point connection between pci host bridge and w83628f. pciclk 44 in t pci bus system clock . pciclk provides timing for all transactions on the pci bus. all other pci signals are sampled on the rising edge of pciclk, and all timing parameters are defined with respect to this edge. pcirst# 47 in t pci reset. w83628f receives pcirst# as a reset from the pci bus. 1. 2 .2 pc/pci interface symbol pin i/o function isareq# 41 out 24t isa bus request. this signal is a point-to-point signal between W83629D and a pci host arbiter . the W83629D asserts this signal according to the pc/pci protocol. isagnt# 42 in t isa bus grant. this signal is a point-to-point signal between W83629D and a pci host bridge ?s secondary bus pcpcignt# signal. W83629D asserts this signal according to the pc/pci protocol. drq [7:5,3:0] 35,33 31,28 26,23 21 in t dma request. the dreq signal indicates that either a slave dma device is requesting dma services, or an isa bus master is requesting use of the isa bus. dack [7:5,3:0]# 34,32 30,27 24,22 20 out 24t dma acknowledge. the dack# signal indicates that either a dma channel or an isa bus master has been granted the isa bus. tc 19 out 24t terminal count. the w83628f asserts tc to dma slaves as a terminal count indicator.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 12 - revision 0.32 1. 2 .3 irq serializer interface symbol pin i/o function serirq 46 i/od 12t serial interrupt requested signals. this signal is for transfer irq mode between parallel irq to serial irq. irq [3:7,9:12,14, 15] 2-6 8-13 in t parallel interrupt requested input. 1. 2 .4 power signals symbol pin i/o function vcc 7, 14, 25 pwr 5v supply. 3vcc 48 pwr 3.3v supply. gnd 1, 18, 29, 43 pwr ground. 1. 2 .5 nc pins symbol pin i/o function nc 36, 37,38, 39, 45 no connection.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 13 - revision 0.32 2. pci configuration registers 2. 1 vid-vendor identification register address offset: 00-01h default value: 1050 h attribute: read only this register is read-only and contains winbond vendor identification number(1050h). 2. 2 did-device identification register address offset: 02-03h default value: 0628h attribute: read only this register is read-only and contains the device identification number(0628h). 2. 3 pcicmd-pci command register address offset: 04-05h default value: 0007h attribute: read/write this register provides control over isa bridge to generate and response to pci cycles properly. when a 0 is written to this register, isa bridge is to be disconnected from pci bus for all accesses except configuration accesses. bit 15:10 reserved. bit 9 fast back to back. this bit always returns a zero. bit 8 serr# enable. =1 enable. =0 disable. bit 7 wait cycle control(not supported). hardwired to zero. bit 6 parity error response(not supported). hardwired to zero. bit 5 vga palette snoop enable(not supported). hardwired to zero. bit 4 memory write and invalidate enable(not supported). hardwir ed to zero.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 14 - revision 0.32 bit 3 parity error response(not supported). hardwired to zero. bit 2 bus master enable. hardwired to one. the isa bridge bus masters are always supported to generate a pci bus master cycle. bit 1 memory space enable. hardwired to one. the isa bridge memory space is always enabled. bit 0 i/o space enable. hardwired to one. the isa bridge i/o space is always enabled. 2. 4 pcists-pci status register address offset: 06-07h default value: 0200h attribute: read/write this register shows status information for pci bus related events. bit 15 detected parity error. hardwired to zero. the isa bridge does not check bus parity. bit 14 signaled system error. this bit is set when isa bridge asserts serr# on pci bus. bit 13 received master abort status. this bit is set when the isa bridge is target aborted as a master on the pci bus. software sets this bit to 0 by writing a 1 to it. bit 12 received target abort status. this bit is set when the isa bridge target aborts a pci transaction as a target. software sets this bit to 0 by writing a 1 to it. bit 11 signaled target abort status. this bit is set when the isa bridge signals a target abort for a pci transaction. software sets this bit to 0 by writing a 1 to it. bit 10:9 devsel# timing. this 2 bits always return a 01b(medium decode). bit 8 data parity detected(not supported). hardwired to zero. bit 7 fast back-to-back(not supported). hardwired to zero.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 15 - revision 0.32 bit 6 66 mhz/ 33 mhz(only support 33 mhz). hardwired to zero. bit 5 user defineable features(not supported). hardwired to zero. bit 4 : 0 reserved. reserved and will returns zero when reading this register. 2. 5 revid-revision identification register address offset: 08h default value: see lastest stepping information attribute: read only this register shows status information for pci bus related events. bit 7 : 0 revision identification number. 2. 6 ccode-calss code register address offset: 09-0bh default value: 060100h attribute: read only the class code register is a read-only register and used to identify the isa bridge. bit 23:16 base class code. 06h = bus bridge bit 15:8 sub-class code. 01h = pci to isa bridge bit 7:0 programming interface. 00h 2. 7 headt-head type register address offset: 0eh default value: 00h attribute: read only the register is a read-only register and used to indicate that the isa bridge configuration space adheres to pci local bus specification. it also indicates that isa bridge is not a multifunction device. bit 7 multifun ction indicator. 0 = not a multifunction device. bit 6:0 layout code. 00h = pci layout type.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 16 - revision 0.32 2. 8 io_rcvr-io recovery register address offset: 40h default value: 4dh attribute: read/write bit 7 sysclk divider. 0 = sysclk is equal to pciclk divided by 4. 1 = sysclk is equal to pciclk divided by 3. bit 6 8-bit i/o recovery enable 0 = disable bits 5:3 setting and uses 3.5 sysclks for 8 bit i/o recovery time. 1 = enable bits 5:3 setting. bit 5:3 8-bit i/o recoverytimes. when bit 6=1 ,this 3-bit field defines the additional number of sysclks added to standard 3.5 sysclk recovery time for 8 bit i/o 000 =0 sysclk 001 =1 sysclk 010 =2 sysclks 011 =3 sysclks 100 =4 sysclks 101 =5 sysclks 110 =6 sysclks 111 = 7 sysclks bit 2 16-bit i/o recovery enable. = 0 ignore bits 1:0 setting and uses 3.5 sysclks for 16-bit i/o recovery time. = 1 the 16-bit i/o recovery time is decided by bits 1:0. bit 1:0 16-bit i/o recovery times. when bit 2=1 ,this 2-bit field defines the additional number of sysclks adde d to standard 3.5 sysclk recovery time for 16 bit i/o = 01 1 sysclk = 10 2 sysclks = 11 3 sysclks = 00 4 sysclks 2. 9 wisa_sts-isa bridge error status register address offset: 42h default value: 00h
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 17 - revision 0.32 attribute: read/write bit 7:3 reserved. bit 2 iochk# pin state. this bit reflects the inverse state of iochk# pin on the isa bus. bit 1 reserved. bit 0 byte lane error. this bit is set if the isa bridge detects an illegal byte lane combination for a pci i/o cycles. 2. 10 wisa_fadc-isa bridge fast decoders control register address offset: 50h default value: 00h attribute: read/write bit 7 enable/disable fast i/o address decoder # 7. bit 6 enable/disable fast i/o address decoder # 6. bit 5 enable/disable fast i/o address decoder # 5. bit 4 enable/disable fast i/o address decoder # 4. bit 3 enable/disable fast i/o address decoder # 3. bit 2 enable/disable fast i/o address decoder # 2. bit 1 enable/disable fast i/o address decoder # 1. bit 0 enable/disable fast i/o addres s decoder # 0. 2. 11 wisa_fad0mc-isa bridge fast decoders # 0 mask control register address offset: 58h default value: 00h attribute: read/write this register is used to mask address bits(a7~a0) for fast address decoder # 0, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignore by the faster address decoder # 0.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 18 - revision 0.32 2. 12 wisa_fad0mc-isa bridge fast decoders # 1 mask control register address offset: 59h default value: 00h attribute: read/write this register is used to mask address bits(a7~a0) for fast address decoder # 1, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignore by the faster address decoder # 1. 2. 13 wisa_fad0mc-isa bridge fast decoders # 2 mask control register address offset: 5ah default value: 00h attribute: read/write this register is used to mask address bits(a7~a0) for fast address decoder # 2, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignore by the faster address decoder # 2. 2. 14 wisa_fad0mc-isa bridge fast decoders # 3 mask control register address offset: 5bh default value: 00h attribute: read/write this register is used to mask address bits(a7~a0) for fast address decoder # 3, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignore by the faster address decoder # 3. 2. 15 wisa_fad0mc-isa bridge fast decoders # 4 mask control register address offset: 5ch default value: 00h attribute: read/write this register is used to mask address bits(a7~a0) for fast address decoder # 4, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignore by the faster address decoder # 4.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 19 - revision 0.32 2. 16 wisa_fad0mc-isa bridge fast decoders # 5 mask control register address offset: 5dh default value: 00h attribute: read/write this register is used to mask address bits(a7~a0) for fast address decoder # 5, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignore by the faster address decoder # 5. 2. 17 wisa_fad0mc-isa bridge fast decoders # 6 mask control register address offset: 5eh default value: 00h attribute: read/write this register is used to mask address bits(a7~a0) for fast address decoder # 6, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignore by the faster address decoder # 6. 2. 18 wisa_fad0mc-isa bridge fast decoders # 7 mask control register address offset: 5fh default value: 00h attribute: read/write this register is used to mask address bits(a7~a0) for fast address decoder # 7, if the corresponding bit of this register is set to a 1, the corresponding address bit(a7~a0) is ignore by the faster address decoder # 7. 2. 19 wisa_fadcb0-isa bridge fast decoders # 0 base address register address offset: 60-61h** default value: 0000h attribute: read/write this register contains the base address for fast address decoder # 0.a **note: 60h is lower byte and 61h is upper byte.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 20 - revision 0.32 2. 20 wisa_fadcb1-isa bridge fast decoders # 1 base address register address offset: 62-63h default value: 0000h attribute: read/write this register contains the base address for fast address decoder # 1. 2. 21 wisa_fadcb2-isa bridge fast decoders # 2 base address register address offset: 64-65h default value: 0000h attribute: read/write this register contains the base address for fast address decoder # 2. 2. 22 wisa_fadcb3-isa bridge fast decoders # 3 base address register address offset: 66-67h default value: 0000h attribute: read/write this register contains the base address for fast address decoder # 3. 2. 23 wisa_fadcb4-isa bridge fast decoders # 4 base address register address offset: 68-69h default value: 0000h attribute: read/write this register contains the base address for fast address decoder # 4. 2. 24 wisa_fadcb5-isa bridge fast decoders # 5 base address register address offset: 6a-6bh default value: 0000h attribute: read/write this register contains the base address for fast address decoder # 5.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 21 - revision 0.32 2. 25 wisa_fadcb6-isa bridge fast decoders # 6 base address register address offset: 6c-6dh default value: 0000h attribute: read/write this register contains the base address for fast address decoder # 6. 2. 26 wisa_fadcb7-isa bridge fast decoders # 6 base address register address offset: 6e-6fh default value: 0000h attribute: read/write this register contains the base address for fast address decoder # 0. 2. 27 wisa_ctrlreg1-isa bridge control register 1 address offset: 70h default value: 0000 01s sb attribute: read/write power-on setting bits bit 1:0 are power-on set by romcs# and hs1. bit 7-6 reserved. bit 5-4 = 00 send ad bus with no step = 01 send ad bus with 2 step = 10 send ad bus with 4 step = 11 reverse bit 3-2 = 00 1mb bios rom positive decode. = 01 2mb bios rom positive decode. = 10 4mb bios rom positive decode. = 11 8mb bios rom positive decode. bit 1 =0 disable high-address bios rom decoder. =1 enable high-address bios rom decoder. this bit can be set/reset by romcs# power-on setting during pcirst# assert. bit 0 =0 normal mode. =1 disable isa bridge subtraction decoder. this bit can be set/reset by hs1 power-on setting during pcirst# assert.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 22 - revision 0.32 2. 28 wisa_ctrlreg2-isa bridge control register 2 address offset: 71h default value: 00h attribute: read/write bit7 =0 enable irq11. =1 disable irq11. bit 6 =0 enable irq10. =1 disable irq10. bit 5 =0 enable irq9. =1 disable irq9. bit 4 =0 enable irq7. =1 disable irq7. bit 3 =0 enable irq6. =1 disable irq6 . bit 2 =0 enable irq5. =1 disable irq5. bit 1 =0 enable irq4. =1 disable irq4. bit 0 =0 enable irq3. =1 disable irq3. 2. 29 wisa_ctrlreg3-isa bridge control register 3 address offset: 72h default value: 00h attribute: read/write bit 7-3 reserved. bit 2 =0 enable irq15. =1 disable irq15. bit 1 =0 enable irq14. =1 disable irq14. bit 0 =0 enable irq12. =1 disable irq12.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 23 - revision 0.32 2. 30 wisa_ctrlreg4-isa bridge control register 4 address offset: 73h default value: 00h attribute: read/write bit7 =0 enable dr q 7. =1 disable drq 7. bit 6 =0 enable drq6. =1 disable drq6. bit 5 =0 enable drq5. =1 disable drq5. bit 4 reserved. bit 3 =0 enable drq 3. =1 disable drq 3. bit 2 =0 enable drq 2. =1 disable drq 2. bit 1 =0 enable drq 1. =1 disable drq 1. bit 0 =0 enable drq 0. =1 disable drq 0. 2. 31 wisa_tstreg-isa bridge test register address offset: 80h default value: 04h attribute: read/write bit 7-5 reserved and should not write data to this register. bit 4 =0 80h port decoding on subtrastive cycle s of lpc i/f. =1 80h port decoding on positive cycles of lpc i/f. this bit must be set 1when lpc i/f is only decoding on positive cycles,but when the bridge is used in piix4 for test set the bit to 0 . bit 3 reserved and should not write data to this register. bit 2-0 000 - 0.8 ns. for winbond internal reference only. 001 - 0.6 ns.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 24 - revision 0.32 010 - 0.4 ns. 011 - 0.2 ns. 100 0 ns. 101 +0.2 ns. 110 +0.4 ns. 111 +0.6 ns.
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 25 - revision 0.32 3. package dimensions 1 for w83628f (128-pin pqfp) l l 1 detail f c e b 1 38 h d d 39 64 h e e 102 65 1.dimension d & e do not include interlead flash. 2.dimension b does not include dambar protrusion/intrusion 3.controlling dimension : millimeter 4.general appearance spec. should be based on final visual inspection spec. . note: seating plane see detail f y a a 1 a 2 128 103 5. pcb layout please use the "mm". symbol b c d e h d h e l y 0 a a l 1 1 2 e 7 0 0.08 1.60 0.95 17.40 0.80 17.20 0.65 17.00 14.10 0.20 0.30 2.87 14.00 2.72 0.50 13.90 0.10 0.10 2.57 0.25 min nom max dimension in mm 0.20 0.15 19.90 20.00 20.10 23.00 23.20 23.40 0.35 0.45 0.003 0 0.063 0.037 0.685 0.031 0.677 0.025 0.669 0.020 0.555 0.008 0.012 0.113 0.551 0.107 0.547 0.004 0.004 0.101 0.010 max nom min dimension in inch 0.006 0.008 7 0.783 0.787 0.791 0.905 0.913 0.921 0.014 0.018
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 26 - revision 0.32 4. package dimensions 2 for W83629D (48-pin lqfp) 2 1 a h d d e b e h e y a a seating plane l l 1 see detail f detail f c 37 48 1 12 13 24 25 36 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 1.40 0.20 0.50 1.00 7.00 9.00 9.00 7.00 --- --- --- 1.60 0.15 1.45 1.35 0.05 0.17 0.27 --- 0.09 0.20 0.45 0.60 0.75 0.08 0 3.5 7 --- --- headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their original owners
pci to isa bridge set w83628f & W83629D preliminary publication release date: jan 1999 - 27 - revision 0.32 5. revision notices. 1998.11.16 add high-address bios rom decoder function(cs#/hs3). (page 7 & page 20) 1998.11.19 change decode range to #fff00000~#ffffffff & #000e00 00~#000fffff. 1999.01.17 supports 3 fully isa compatible slots without buffering rename hs3. it is renamed to romcs# in w83628f,and nc in W83629D. 1999.04.21 indicate the bit 4 of offset address 80h is used to enable 80h port decoding when only positive decoding switched of lpc i/f.

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